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Upcoming trainings ... Interested? Please contact mianyang@threshing-floor.net for details.
Introduction to Integrated Circuit (IC) Design
Open for Enrollment
Open for Enrollment
Exciting News: Next Intake for “Introduction to IC Design” is Now Open!
The National Semiconductor Strategy (NSS) has set a bold vision — positioning Malaysia to move from a Back-End powerhouse to a Front-End IC Design leader in Southeast Asia. However, this ambition can only be realized with skilled talent ready to take on higher-value roles.
I’m pleased to announce the next intake of the Introduction to IC Design training program. This is a great opportunity for engineers and VLSI professionals who want to:
Understand the end-to-end IC Design flow
Gain hands-on insight into RTL coding, simulation, synthesis, and netlist generation
Align their skills with industrial demands and Malaysia’s NSS roadmap
Select your Session:
20 or 27 May 2026 (1-day intensive training)
Whether you are
· already working in specific area of IC design and looking for the big picture
· From semiconductor manufacturing, testing, quality, or any related field and want better alignment with the design team
· Or simply want to build a strong foundation in IC Design
This is the perfect place.
Secure your spot now!
WhatsApp: Sean Lee, Chew – 012-407 2527
IP RTL Design
Open for Enrollment
Open for Enrollment
Announcing: IP RTL Design – 2-Day Intensive Training
In today’s AI-driven semiconductor landscape, IP RTL Design has become the most critical and influential stage in the entire IC lifecycle.
Mastering production-quality IP RTL Design means you are no longer just writing code — you are bridging the gap between high-level architectural vision and silicon-ready, reusable, low-risk RTL — the true foundation for first-pass silicon success and long-term competitiveness.
Who Should Attend
This training is designed for:
Hardware & RTL Design Engineers / VLSI Professionals looking to upskill
Fresh Graduates aiming to build strong, industry-ready RTL foundations
Mid-level Engineers transitioning into IP design roles
R&D and SoC Teams focused on accelerating development cycles and reducing tapeout risks
Limited seats available.
For registration and further details, please contact:
Sean Lee, Chew WhatsApp 012-407 2527
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